dc.contributor.author |
Salcic, Zoran |
en |
dc.contributor.author |
Hui, D |
en |
dc.contributor.author |
Roop, Parthasarathi |
en |
dc.contributor.author |
Biglari-Abhari, M |
en |
dc.date.accessioned |
2012-02-23T00:05:28Z |
en |
dc.date.issued |
2006 |
en |
dc.identifier.citation |
Microprocessors and Microsystems 30(2):72-85 2006 |
en |
dc.identifier.issn |
0141-9331 |
en |
dc.identifier.uri |
http://hdl.handle.net/2292/11660 |
en |
dc.description.abstract |
Embedded systems are typically heterogeneous requiring interacting hardware and software components, are locally synchronous while being globally asynchronous and combine both control and data dominated blocks. Conventional architectures and hardware–software platforms do not directly support such heterogeneity leading to complex design flow and verification process for such systems. This paper presents a new architecture for heterogeneous embedded systems called HiDRA based on multiple reactive processor cores. The architecture supports globally asynchronous locally synchronous systems with a mix of data-dominated and control-dominated behaviors. The reactive processor cores implement Esterel-like computation with architectural support for signal polling, emission and preemption. HiDRA also provides primitives for communication and synchronization between concurrent processes. A low level (concurrent reactive assembly) language has been specified to model embedded applications, which are executable directly on the HiDRA platform. The first implementations with up to four reactive processors have been done on the standard FPGAs. Performance comparison with a typical application realized from system level language ECL reveals significant speedup and reduction in code size. |
en |
dc.publisher |
Elsevier |
en |
dc.relation.ispartofseries |
Microprocessors and Microsystems |
en |
dc.rights |
Items in ResearchSpace are protected by copyright, with all rights reserved, unless otherwise indicated. Previously published items are made available in accordance with the copyright policy of the publisher. Details obtained from: http://www.sherpa.ac.uk/romeo/issn/0141-9331/ |
en |
dc.rights.uri |
https://researchspace.auckland.ac.nz/docs/uoa-docs/rights.htm |
en |
dc.title |
HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems |
en |
dc.type |
Journal Article |
en |
dc.identifier.doi |
10.1016/j.micpro.2005.05.001 |
en |
pubs.issue |
2 |
en |
pubs.begin-page |
72 |
en |
pubs.volume |
30 |
en |
dc.rights.holder |
Copyright: Elsevier |
en |
pubs.end-page |
85 |
en |
dc.rights.accessrights |
http://purl.org/eprint/accessRights/RestrictedAccess |
en |
pubs.subtype |
Article |
en |
pubs.elements-id |
40311 |
en |
pubs.org-id |
Engineering |
en |
pubs.org-id |
Department of Electrical, Computer and Software Engineering |
en |
pubs.record-created-at-source-date |
2010-09-01 |
en |