Efficient Ray Tracing on FPGAs

Abstract

Ray tracing is a computationally intensive task required by movie-makers to create the highly realistic images they require for motion pictures. GPUs currently dominate as hardware accelerators in the multi-billion dollar movie industry. However, the flexibility and power efficiency of FPGAs offer high potential to applications with many levels of parallelism, such as ray tracing. This thesis investigates and proposes an FPGA platform to easily and efficiently explore parallelism in ray tracing on FPGAs, to decrease the productivity gap between the exponentially increasing amount of logic found on FPGAs and the number of man-hours taken to develop applications for them, fulfilling the first objective of this research. Various aspects and components of the platform that are critical for the ray tracing performance are then deeply investigated. Two essential parts of ray tracing performance are the processes of determining if a ray intersects with a scene primitive, and determining if a ray intersects with an acceleration hierarchy bounding box. Deep, parallel floating-point pipelines for these ray-triangle and ray-box intersection tests are proposed. Both pipelines are evaluated and show potential for scalability and improved performance over other accelerated implementations. Traversal of individual rays are independent and can be parallelised. The platform scales the number of traversal units implemented to exploit this, with a key component to their scalability the implementation of the priority queue contained within them. A novel hybrid hardware combination of a single-cycle queue and a heap is presented that combines the speed of a single-cycle queue with the scalability of a heap. An innovative method to simulate different priority queue workloads is developed to evaluate queue performance under different conditions. Optimisations are made to the heap for efficiency and scalability on the ray tracing platform. Memory bandwidth on the proposed platform is identified as a bottleneck, with a cache being a good candidate to alleviate bandwidth requirements. Memory access patterns to the acceleration hierarchy and scene primitives during ray tracing of four typical scenes on the platform are explored, leading to development of a novel node cache replacement policy. Evaluation shows that the replacement policy can provide a good performance increase for small cache sizes and may work well as a complimentary cache along side a direct mapped cache, and that the implementation of a node and primitive cache successfully alleviates the memory bandwidth bottleneck. The presented floating-point intersection pipelines, heap implementation and optimisations, and ray tracing cache architecture fulfil the second objective of the research: to provide building blocks and optimisations that enable ray tracing efficiency on FPGAs. An extensive experimental evaluation of the proposed platform on real hardware for four typical scenes is performed, including investigating the effect of priority queue type on performance and scalability, the impact of a cache on platform performance and the performance of the platform in relation to a CPU and GPU. The evaluation showed that scaling the number of traversal units with a cache provides an increase in performance over all scenes, the FPGA platform has better power efficiency than both the CPU and the GPU over all scenes and the FPGA platform has better bandwidth efficiency than both the CPU and the GPU over all scenes, with further improvements possible in all areas with the use of more current FPGA technology. This evaluation fulfils the final objective of the research: to demonstrate that FPGAs have a great potential for power and bandwidth efficiency when accelerating ray tracing. Given the demonstrated potential of FPGAs as hardware accelerators for ray tracing, the proposed platform enables easy evaluation of newer FPGA technologies and ray tracing techniques, providing an important stepping-stone to researchers for further advances.