A methodology for the optimisation and synthesis of digital FPGA-based circuits

Abstract

This thesis examines the development and analysis of a methodology for designing and optimising digital FPGA-based circuits. The focus is on assisting the designer at a very high level – as either a pre-processor or as a specific solution design that can be reapplied. The study includes an investigation of related research, methods, and techniques. Initially, a synthesiser is developed to produce hardware description language listings for stochastic neural networks. This highlights the advantages and disadvantages of special-purpose synthesis. In particular, the close hardware mapping of stochastic summation and sigmoidal activation functions is described. The second synthesiser is developed for general purpose synthesis. It is based on synchronous sub-circuit modules and supports hierarchical designs. The modules are described in static libraries or in extensions to the synthesiser core that create the modules during synthesis. The modules can be of various data types including parallel, serial, and stochastic representations. The synthesiser supports hardware resource-sharing to trade-off cell count and cycle count. It analyses the circuits in terms of their pipelined data flow and operating latency. A separate module scheduler and controller circuit is synthesised as part of the synthesiser's operation. A genetic algorithm is tailored to the problem of digital circuit optimisation through the development of specific structures and procedures. In particular, a concise encoding of the circuit is developed that the genetic algorithm can manipulate. Specific crossover and mutation mechanisms are also developed to complement the functionality of the synthesiser. The searches are effected by altering module data type, hardware resource sharing, and module implementation version. A fitness function is derived that makes use of a number of optimisation parameters to objectively evaluate each particular circuit. The features of each circuit are calculated and estimated during the analysis phase. This includes an estimate of cell-count for a particular target technology, for which the concept of a hardware compression factor is introduced. The developed software implementations are examined in terms of the software development process. Various engineering issues are discussed along with details of the development strategies employed. The synthesis software is designed for robustness, low development time, and low debugging time. The cost is a less-than-optimal operating speed of the synthesis and optimisation code. Two detailed case studies are examined to show the synthesis and optimisation performance. A formula is derived to calculate the quantitative extents of the design spaces being searched. The optimiser is shown to converge to 'fit' solutions-in terms of the desired constraints and the objective fitness function. Clustering of solution points in the design spaces is observed. These are generally narrow in terms of cycle count and considerable in terms of cell count. Trends are apparent across the design space showing that module data type and resource sharing are correlated to cell-count and cycle-count. Different circuit optimisations produce different correlations such that an overall generalisation was not appropriate.