Modular and parallel code generation for hybrid systems

Abstract

Cyber physical systems (CPS) integrate with computational and physical components, and have great social and economic impacts. One of the main challenges in designing CPS is due to its inherent safety criticality characteristic. If such kind of system is unreliable, it can lead to catastrophic damages. Extensive closed-loop validation is essential for designing these kinds of safety critical systems. A simulation of the actual physical process/plant is composed with the digital controller for validation. To this end, hybrid systems - a large subset of CPS are modeled as Hybrid Input Output Automata (HIOAs), which is a well-defined formal model. However, efficient execution of HIOA models is one of the major hurdles in adoption of HIOA for validation of large-scale industrial applications. The existing techniques for simulation of the actual plant modeled as a network of HIOAs lack modular compilation, which is essential for effective parallel execution. To enable efficient execution of high-fidelity plant/process models, this thesis proposes a new compilation framework that enables modular compilation and parallelization for a network of HIOAs. The simulation of the cardiac conduction system, a complex system with over 3000 HIOAs is used as a case-study and running example to describe the proposed methodology. A parallelizing compiler for a network of HIOAs that leverages Cilk and OpenMP libraries are developed in this thesis. The study of the feasibility of parallelizing a network of HIOAs is carried out and the analysis of the efficiency of parallelization is presented. Several benchmarks from different engineering domains are used for evaluation. The experimental results show on average, four threads executing a network of HIOAs in parallel gives 1.4× speedup over sequential execution, with a maximum speedup of around 2.5×. When the number of HIOAs in the network is large enough, the greater number of threads forked leads to greater speedup. This is restricted by the platform with a maximum of four available threads. Additionally, the results show that the compiler for modular and parallel code generation developed in this research achieves an improvement on the execution efficiency of HIOA models.