Abstract:
This paper concerns computer architectures and computer designs in which registers are
virtual, that is, where registers do not necessarily correspond exactly to a real fast
storage array, in particular where there are many more registers addressable than fast
storage elements implemented. There are many architectures where registers are to a
greater or lesser extent virtual. One scheme, where the in-use registers are managed as a
set associative cache, is explored in some depth - it is seen that such a scheme is not as
unreasonable as it might first appear.
