dc.contributor.author |
Doran, R.W. |
en |
dc.contributor.author |
Fenwick, P. |
en |
dc.contributor.author |
Qun, Z. |
en |
dc.date.accessioned |
2009-04-08T04:02:48Z |
en |
dc.date.available |
2009-04-08T04:02:48Z |
en |
dc.date.issued |
1991-10 |
en |
dc.identifier.citation |
Computer Science Technical Reports 057 (1991) |
en |
dc.identifier.issn |
1173-3500 |
en |
dc.identifier.uri |
http://hdl.handle.net/2292/3463 |
en |
dc.description.abstract |
This paper concerns computer architectures and computer designs in which registers are
virtual, that is, where registers do not necessarily correspond exactly to a real fast
storage array, in particular where there are many more registers addressable than fast
storage elements implemented. There are many architectures where registers are to a
greater or lesser extent virtual. One scheme, where the in-use registers are managed as a
set associative cache, is explored in some depth - it is seen that such a scheme is not as
unreasonable as it might first appear. |
en |
dc.publisher |
Department of Computer Science, The University of Auckland, New Zealand |
en |
dc.relation.ispartofseries |
Computer Science Technical Reports |
en |
dc.rights.uri |
https://researchspace.auckland.ac.nz/docs/uoa-docs/rights.htm |
en |
dc.source.uri |
http://www.cs.auckland.ac.nz/staff-cgi-bin/mjd/csTRcgi.pl?serial |
en |
dc.title |
Virtual Registers |
en |
dc.type |
Technical Report |
en |
dc.subject.marsden |
Fields of Research::280000 Information, Computing and Communication Sciences |
en |
dc.rights.holder |
The author(s) |
en |