Design & Implementation of Physical Layer in FPGA Technology for Wireless Sensor Network

Abstract

This paper presents a mathematical model of a low power consumption transceiver and its FPGA design based on the DSSS BPSK modulation. To analyse the performance of the designed system, a mathematical model of the communication environment is developed. The system is analysed assuming the presence of AWGN and Rayleigh flat fading in the channel. The proposed transceiver is simulated according to this theoretical model. The proposed transceiver is then implemented on a hardware level using FPGA technology and the VHDL hardware description language. The resulting system is analysed using models of the environment, and produced satisfactory performances. It was shown that the BER characteristics of the designed system match very well with simulation and theory.