Abstract:
System-on-a-chip (SoC) designs have gained immense popularity as they provide designers
with the ability of integrating all components (called IPs) of an application-specific computer
system onto a single chip. However, one of the main bottlenecks of the SoC design
cycle is the validation of complex designs. As system size grows, validation time increases
beyond manageable limits. It is desirable that design inconsistences are found and fixed
early in the design process, as validation overheads are significantly higher after IPs are
integrated. This thesis presents a range of techniques for the automatic verification and
design of SoCs that aim to reduce post-integration validation costs.
Firstly, local module checking algorithm, a practical implementation of module checking,
is presented. This technique allows for the comprehensive verification of IPs such
that they guarantee the satisfaction of critical specifications regardless of the SoC they
are used in. Local module checking is shown to be able to validate IPs in much lesser
time on average than global module checking, and can help in handling many important
validation tasks much before the integration stage.
Next, a number of protocol conversion techniques that assist in the composition of IPs
with incompatible protocols is presented. The inconsistencies between IP protocols, called
mismatches, are bridged by the automatic generation of some extra glue-logic, called a
converter. Converters generated by the proposed techniques can handle control, datawidth
and clock mismatches between multiple IPs in a unified manner. These approaches
ensure that the integration of IPs is correct-by-construction, such that the final system is
guaranteed to satisfy key specifications without the need for further validation.
Finally, a technique for automatic IP reuse using forced simulation is presented, which
involves automatically generating an adaptor that guides an IP such that it satisfies desired
specifications. The proposed technique can generate adaptors in many cases where
existing IP techniques fail. As it is guaranteed that reused IPs satisfy desired specifications,
post-integration validation costs are significantly reduced.
For each proposed technique, a comprehensive set of results is presented that highlights
the significance of the solution. It is noted that the proposed approaches can help
automate SoC design and achieve significant savings in post-integration validation costs.