dc.contributor.advisor |
Sinnen, O |
en |
dc.contributor.author |
Wang, Haomiao |
en |
dc.date.accessioned |
2019-03-12T22:28:00Z |
en |
dc.date.issued |
2019 |
en |
dc.identifier.uri |
http://hdl.handle.net/2292/45936 |
en |
dc.description.abstract |
The Square Kilometre Array (SKA) will be the world’s largest radio telescope array when it is finished. To keep processing the huge number of signals received from hundreds of antennas, hardware accelerators with high-performance computing and power efficient attributes are required. Given the flexibility, power-efficient, and high-performance computing requirements, the Field Programmable Gate Arrays (FPGAs) with their large amount of low latency and power-efficiency logic processing cells and blocks are an ideal type of acceleration hardware for the pulsar search engine of the SKA central signal processing system. However, FPGAs are not widely adopted by radio astronomy scientists and software engineers due to their lack of hardware expertise. Furthermore, FPGAs have a limited usable area and traditional synthesis flows might become problems when combing and implementing complex data-intensive and compute-intensive signal processing modules. This thesis investigates the acceleration of pulsar search modules on high-end FPGAs using high-level synthesis tools. Two pulsar search modules, the FT convolution module and the harmonic-summing module, are optimised and implemented using OpenCL. For the FT convolution module, the overlap algorithms are employed to split the tasks and make them fit on a specific FPGA device. Regarding the harmonic-summing module, the large number of irregular accesses to off-chip memory are optimised. Besides optimising a single module, the combination of well-optimised modules using pipeline computing on multiple FPGA devices is investigated. The experimental evaluations on different series Intel high-end FPGAs and different types of platforms such as GPUs and multi-core processors show that multiple FPGA devices provide higher power efficiency than CPUs and GPUs in implementing the same kernel codes. Three Stratix V or Arria 10 FPGAs have a higher value in performance per watt than one GPU in processing the FDAS module. Furthermore, FPGA implementations can deliver a significant performance improvement over multi-core processors and a comparable performance with that of GPU implementations. |
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dc.publisher |
ResearchSpace@Auckland |
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dc.relation.ispartof |
PhD Thesis - University of Auckland |
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dc.relation.isreferencedby |
UoA99265146213902091 |
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dc.rights |
Items in ResearchSpace are protected by copyright, with all rights reserved, unless otherwise indicated. Previously published items are made available in accordance with the copyright policy of the publisher. |
en |
dc.rights.uri |
https://researchspace.auckland.ac.nz/docs/uoa-docs/rights.htm |
en |
dc.rights.uri |
http://creativecommons.org/licenses/by-nc-sa/3.0/nz/ |
en |
dc.title |
Acceleration of FDAS Module with Reconfigurable Hardware Using OpenCL |
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dc.type |
Thesis |
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thesis.degree.discipline |
Electrical and Electronic Engineering |
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thesis.degree.grantor |
The University of Auckland |
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thesis.degree.level |
Doctoral |
en |
thesis.degree.name |
PhD |
en |
dc.rights.holder |
Copyright: The author |
en |
dc.rights.accessrights |
http://purl.org/eprint/accessRights/OpenAccess |
en |
pubs.elements-id |
765892 |
en |
pubs.org-id |
Engineering |
en |
pubs.org-id |
Department of Electrical, Computer and Software Engineering |
en |
pubs.record-created-at-source-date |
2019-03-13 |
en |
dc.identifier.wikidata |
Q112950741 |
|