A Novel Compiler for Synchronous Neural Networks to Hardware

Abstract

Cyber-Physical Systems (CPS), such as autonomous vehicles, are using machine learning for decision making. In particular, complex computer vision-based algorithms are being used for safety-critical tasks such as traffic sign and pedestrian detection. Such algorithms rely on Artificial Neural Networks (ANNs) for the implementation of machine vision. In these safety critical applications, where a failure in operation can lead to severe negative consequences, it is of paramount importance that the machine learning modules provide functional and timing guarantees. While many formal approaches have been recently proposed for ensuring functional correctness of machine learning modules, the issue of timing correctness has received scant attention. The key problem is that these ANNs are realised in software, where ensuring correct timing is very complex. It is especially difficult to compute the worst-case timing bound of such systems so as to ensure that the underlying implementation meets all necessary timing requirements. The worst-case timing bound is usually computed using static analysis techniques and the associated methods are known as Worst Case Execution Time (WCET) analysis.This thesis explores the hardware avenue for machine learning modules to ensure real-time implementations. First, we use Keras library to perform the learning phase of a given ANN module, so that all weights are statically known. This thesis then proposes a new compiler, which compiles networks from Keras Neural Network library to hardware to allow for timing analysis of a system. In the developed approach, we compile networks of ANNs, called Meta Neural Networks, to hardware implementations using a new synchronous semantics for their execution. The developed semantics enables compilation of Meta Neural Networks (MNNs) to a parallel hardware implementation involving limited hardware resources. The developed compiler is semantics driven and guarantees that the generated implementation is deterministic and time predictable. The compiler also provides a better alternative for the realisation of nonlinear functions in hardware. Overall, we show that the developed approach is significantly more efficient than a software approach, without the burden of complex algorithms needed for software Worst Case Execution Time analysis. We also show that the generated solution performs inference similarly to its software implementation counterpart.