Abstract:
Until recently, almost all methods for target tracking and estimation have followed the
algorithmic path. The use of complex algorithms, such as Kalman-filter-based algorithms,
generally require high speed and a high degree of parallelism, which are beyond the
capabilities of available computational resources. The customisation features of field
programmable logic devices (FPLDs) can be used to flexibly customise the
hardware/software in FPLDs to meet the different requirements of system speed and
system complex functions. FPLD-based customisable digital systems are investigated and
developed to improve both performance and methodology for implementing complex
multiple target tracking (MTT) algorithms.
The methodology of the scalar-based direct algorithm mapping is proposed to provide a
simple method to implement complex computing algorithms into the FPLD hardware
circuit. The comprehensive comparison with the matrix-based systolic algorithm
engineering method for systolic array implementation shows the superiority of the scalar-
based direct algorithm mapping method in MTT applications. Two basic architectures for
the implementation of Kalman-filter-based algorithms in FPLDs are presented. Fully-
hardware-type architecture provides hardware efficiency that can reach the highest
performance. Hardware/software-type architecture that includes hardware part and
software part provides hardware efficiency and software flexibility. Hardware-type Kalman
filter coprocessor (HKFC) and hardware/software-type Kalman filter application-specific
processor (KFASP) have been designed and implemented in a single FPLD device. Their
performances are two to four orders of magnitude faster than the other known
implementations of the Kalman filter. As a further step in evolution, an adaptive system,
FPLD-based adaptive tracking estimation computer (FATEC), is also proposed. It has
several hardware-type functional units to provide the high performance as well as the
adaptability to perform various functions in the adaptive MTT algorithm. The
hardware/software trade-offs in its implementation have been studied and their
performances have been evaluated. The criteria for optimising hardware/software trade
offs have been extracted.