A Network-on-Chip simulation framework

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dc.contributor.advisor Biglari-Abhari, M en
dc.contributor.author Hussain, Syed en
dc.date.accessioned 2011-07-17T22:44:15Z en
dc.date.issued 2011 en
dc.identifier.uri http://hdl.handle.net/2292/6915 en
dc.description Full text is available to authenticated members of The University of Auckland only. en
dc.description.abstract Network-on-Chip (NoC) interconnection is expected to have a promising future for Multi-Processor-System-on-Chip scalability and performance. In order to explore NoC platforms at higher level of abstraction we have developed highly parameterized building blocks for NoC modeling using SystemC. The building blocks have been built using OCP-IP wrappers so heterogeneous cores can be easily mapped. Packet based worm-hole switching for communication has been chosen for NoC communication. Minimal path routing algorithm has been adopted for routing of this communication. Simulation results show that 26 cycles are required for end-to-end packet delivery of size 3 flits in a 4x4 mesh network. Using these tools various case studies on NoC can be explored by adding some additional elements. Issues such as cache coherency and memory consistency in NoC can create bottleneck in development of NoC based systems. This opens research challenges and opportunities since conventional approaches cannot be applied directly. Some generic scenarios are created using these simulation tools that highlights these issues. By adding some additional information such as coherency flits and synchronization flits the above mentioned issues can be addressed. A two dimensional 2x2 mesh in NoC based system is for this purpose. en
dc.publisher ResearchSpace@Auckland en
dc.relation.ispartof Masters Thesis - University of Auckland en
dc.rights Restricted Item. Available to authenticated members of The University of Auckland. en
dc.rights.uri https://researchspace.auckland.ac.nz/docs/uoa-docs/rights.htm en
dc.rights.uri http://creativecommons.org/licenses/by-nc-sa/3.0/nz/ en
dc.title A Network-on-Chip simulation framework en
dc.type Thesis en
thesis.degree.grantor The University of Auckland en
thesis.degree.level Masters en
dc.rights.holder Copyright: The author en
pubs.author-url http://hdl.handle.net/2292/6915 en
pubs.elements-id 214841 en
pubs.record-created-at-source-date 2011-07-18 en


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