Hardware Acceleration for the Simulation of Processor Designs

Abstract

Modern integrated circuits feature a far higher level of complexity than was previously practicable, made possible with improvements in manufacturing technology. Processor architectures have improved in direct correlation with the increase in available logic resources, resulting in increased performance and contributing to increases in design complexity. The increase in complexity has resulted in an increase in the requirements for simulation. Simulation is performed to ensure designs are accurate and to gain indicators of performance, without requiring processors to actually be manufactured, as this can pose a great cost. Because of power issues related to the shrinking of designs, processors have had to move to a multi-core model. This has resulted in a relative decrease in the performance of software based simulations, which are inherently single threaded. A relative decrease in simulation performance has resulted from designs becoming more complex while simulator performance remains fairly static. An alternative approach has been suggested that makes use of high level hardware description languages, for example Bluespec System Verilog, to succinctly describe architectures or models thereof. The models are synthesised and run on FPGAs, which should offer increased simulation speed relative to software based simulation. The time taken to design, implement and verify the simulator, however, will increase even with the high level features available with languages like Bluespec System Verilog. An analysis of two simulators is presented, along with a description of the specific architectures they model. A software based simulator, the existing SimpleScalar toolset, is discussed, as is a hardware based implementation. This implementation has been designed with Bluespec System Verilog and features a five stage RISC pipeline. Both simulators make use of the PISA instruction set and, as a result, identical binaries can be run for comparison purposes. A series of benchmarks were run under both simulators and the results were analysed. The hardware implementation was shown to be significantly faster than the software based simulator, although some benchmarks could not be fully simulated due to implementation limitations.